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Searched refs:GCC_PCIE_1_BCR (Results 1 – 25 of 33) sorted by relevance

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/openbmc/linux/include/dt-bindings/reset/
H A Dqcom,gcc-apq8084.h92 #define GCC_PCIE_1_BCR 83 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,sdx75-gcc.h170 #define GCC_PCIE_1_BCR 3 macro
H A Dqcom,gcc-sc7280.h211 #define GCC_PCIE_1_BCR 2 macro
H A Dqcom,gcc-sm8450.h208 #define GCC_PCIE_1_BCR 9 macro
H A Dqcom,sm8550-gcc.h192 #define GCC_PCIE_1_BCR 8 macro
H A Dqcom,gcc-sdm845.h207 #define GCC_PCIE_1_BCR 2 macro
H A Dqcom,gcc-sm8150.h219 #define GCC_PCIE_1_BCR 6 macro
H A Dqcom,gcc-sm8250.h221 #define GCC_PCIE_1_BCR 9 macro
H A Dqcom,gcc-sm8350.h223 #define GCC_PCIE_1_BCR 9 macro
H A Dqcom,gcc-sc8180x.h256 #define GCC_PCIE_1_BCR 6 macro
H A Dqcom,sa8775p-gcc.h274 #define GCC_PCIE_1_BCR 12 macro
H A Dqcom,gcc-msm8996.h321 #define GCC_PCIE_1_BCR 81 macro
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sdx75.c2866 [GCC_PCIE_1_BCR] = { 0x67000 },
H A Dgcc-sm8450.c3180 [GCC_PCIE_1_BCR] = { 0x9d000 },
H A Dgcc-sm8550.c3254 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-sm8250.c3545 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-apq8084.c3589 [GCC_PCIE_1_BCR] = { 0x1b40 },
H A Dgcc-sc7280.c3388 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-msm8996.c3558 [GCC_PCIE_1_BCR] = { 0x6d000 },
H A Dgcc-sm8350.c3720 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-sm8150.c3718 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-sdm845.c3875 [GCC_PCIE_1_BCR] = { 0x8d000 },
H A Dgcc-sa8775p.c4634 [GCC_PCIE_1_BCR] = { 0x77000 },
H A Dgcc-sc8180x.c4495 [GCC_PCIE_1_BCR] = { 0x8d000 },
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8775p.dtsi2565 resets = <&gcc GCC_PCIE_1_BCR>;

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