Home
last modified time | relevance | path

Searched refs:FW_MPU_DDR_SCR_WRITEL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c180 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
181 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); in sdram_mmr_init_full()
184 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, in sdram_mmr_init_full()
186 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT); in sdram_mmr_init_full()
189 FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, in sdram_mmr_init_full()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfirewall_s10.h117 #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ macro