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Searched refs:FW_BLC_SELF_EN (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
H A Dpsb_intel_reg.h567 #define FW_BLC_SELF_EN (1<<15) macro
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c149 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
150 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
162 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
163 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
164 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in _intel_set_memory_cxsr()
3620 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
H A Dintel_display_debugfs.c69 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h1071 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ macro