1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Faraday FTGMAC100 Gigabit Ethernet
4  *
5  * (C) Copyright 2009-2011 Faraday Technology
6  * Po-Yu Chuang <ratbert@faraday-tech.com>
7  */
8 
9 #ifndef __FTGMAC100_H
10 #define __FTGMAC100_H
11 
12 #define FTGMAC100_OFFSET_ISR		0x00
13 #define FTGMAC100_OFFSET_IER		0x04
14 #define FTGMAC100_OFFSET_MAC_MADR	0x08
15 #define FTGMAC100_OFFSET_MAC_LADR	0x0c
16 #define FTGMAC100_OFFSET_MAHT0		0x10
17 #define FTGMAC100_OFFSET_MAHT1		0x14
18 #define FTGMAC100_OFFSET_NPTXPD		0x18
19 #define FTGMAC100_OFFSET_RXPD		0x1c
20 #define FTGMAC100_OFFSET_NPTXR_BADR	0x20
21 #define FTGMAC100_OFFSET_RXR_BADR	0x24
22 #define FTGMAC100_OFFSET_HPTXPD		0x28
23 #define FTGMAC100_OFFSET_HPTXR_BADR	0x2c
24 #define FTGMAC100_OFFSET_ITC		0x30
25 #define FTGMAC100_OFFSET_APTC		0x34
26 #define FTGMAC100_OFFSET_DBLAC		0x38
27 #define FTGMAC100_OFFSET_DMAFIFOS	0x3c
28 #define FTGMAC100_OFFSET_REVR		0x40
29 #define FTGMAC100_OFFSET_FEAR		0x44
30 #define FTGMAC100_OFFSET_TPAFCR		0x48
31 #define FTGMAC100_OFFSET_RBSR		0x4c
32 #define FTGMAC100_OFFSET_MACCR		0x50
33 #define FTGMAC100_OFFSET_MACSR		0x54
34 #define FTGMAC100_OFFSET_TM		0x58
35 #define FTGMAC100_OFFSET_PHYCR		0x60
36 #define FTGMAC100_OFFSET_PHYDATA	0x64
37 #define FTGMAC100_OFFSET_FCR		0x68
38 #define FTGMAC100_OFFSET_BPR		0x6c
39 #define FTGMAC100_OFFSET_WOLCR		0x70
40 #define FTGMAC100_OFFSET_WOLSR		0x74
41 #define FTGMAC100_OFFSET_WFCRC		0x78
42 #define FTGMAC100_OFFSET_WFBM1		0x80
43 #define FTGMAC100_OFFSET_WFBM2		0x84
44 #define FTGMAC100_OFFSET_WFBM3		0x88
45 #define FTGMAC100_OFFSET_WFBM4		0x8c
46 #define FTGMAC100_OFFSET_NPTXR_PTR	0x90
47 #define FTGMAC100_OFFSET_HPTXR_PTR	0x94
48 #define FTGMAC100_OFFSET_RXR_PTR	0x98
49 #define FTGMAC100_OFFSET_TX		0xa0
50 #define FTGMAC100_OFFSET_TX_MCOL_SCOL	0xa4
51 #define FTGMAC100_OFFSET_TX_ECOL_FAIL	0xa8
52 #define FTGMAC100_OFFSET_TX_LCOL_UND	0xac
53 #define FTGMAC100_OFFSET_RX		0xb0
54 #define FTGMAC100_OFFSET_RX_BC		0xb4
55 #define FTGMAC100_OFFSET_RX_MC		0xb8
56 #define FTGMAC100_OFFSET_RX_PF_AEP	0xbc
57 #define FTGMAC100_OFFSET_RX_RUNT	0xc0
58 #define FTGMAC100_OFFSET_RX_CRCER_FTL	0xc4
59 #define FTGMAC100_OFFSET_RX_COL_LOST	0xc8
60 
61 /*
62  * Interrupt status register & interrupt enable register
63  */
64 #define FTGMAC100_INT_RPKT_BUF		(1 << 0)
65 #define FTGMAC100_INT_RPKT_FIFO		(1 << 1)
66 #define FTGMAC100_INT_NO_RXBUF		(1 << 2)
67 #define FTGMAC100_INT_RPKT_LOST		(1 << 3)
68 #define FTGMAC100_INT_XPKT_ETH		(1 << 4)
69 #define FTGMAC100_INT_XPKT_FIFO		(1 << 5)
70 #define FTGMAC100_INT_NO_NPTXBUF	(1 << 6)
71 #define FTGMAC100_INT_XPKT_LOST		(1 << 7)
72 #define FTGMAC100_INT_AHB_ERR		(1 << 8)
73 #define FTGMAC100_INT_PHYSTS_CHG	(1 << 9)
74 #define FTGMAC100_INT_NO_HPTXBUF	(1 << 10)
75 
76 /* Interrupts we care about in NAPI mode */
77 #define FTGMAC100_INT_BAD  (FTGMAC100_INT_RPKT_LOST | \
78 			    FTGMAC100_INT_XPKT_LOST | \
79 			    FTGMAC100_INT_AHB_ERR   | \
80 			    FTGMAC100_INT_NO_RXBUF)
81 
82 /* Normal RX/TX interrupts, enabled when NAPI off */
83 #define FTGMAC100_INT_RXTX (FTGMAC100_INT_XPKT_ETH  | \
84 			    FTGMAC100_INT_RPKT_BUF)
85 
86 /* All the interrupts we care about */
87 #define FTGMAC100_INT_ALL (FTGMAC100_INT_RXTX  |  \
88 			   FTGMAC100_INT_BAD)
89 
90 /*
91  * Interrupt timer control register
92  */
93 #define FTGMAC100_ITC_RXINT_CNT(x)	(((x) & 0xf) << 0)
94 #define FTGMAC100_ITC_RXINT_THR(x)	(((x) & 0x7) << 4)
95 #define FTGMAC100_ITC_RXINT_TIME_SEL	(1 << 7)
96 #define FTGMAC100_ITC_TXINT_CNT(x)	(((x) & 0xf) << 8)
97 #define FTGMAC100_ITC_TXINT_THR(x)	(((x) & 0x7) << 12)
98 #define FTGMAC100_ITC_TXINT_TIME_SEL	(1 << 15)
99 
100 /*
101  * Automatic polling timer control register
102  */
103 #define FTGMAC100_APTC_RXPOLL_CNT(x)	(((x) & 0xf) << 0)
104 #define FTGMAC100_APTC_RXPOLL_TIME_SEL	(1 << 4)
105 #define FTGMAC100_APTC_TXPOLL_CNT(x)	(((x) & 0xf) << 8)
106 #define FTGMAC100_APTC_TXPOLL_TIME_SEL	(1 << 12)
107 
108 /*
109  * DMA burst length and arbitration control register
110  */
111 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x)	(((x) & 0x7) << 0)
112 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x)	(((x) & 0x7) << 3)
113 #define FTGMAC100_DBLAC_RX_THR_EN	(1 << 6)
114 #define FTGMAC100_DBLAC_RXBURST_SIZE(x)	(((x) & 0x3) << 8)
115 #define FTGMAC100_DBLAC_TXBURST_SIZE(x)	(((x) & 0x3) << 10)
116 #define FTGMAC100_DBLAC_RXDES_SIZE(x)	(((x) & 0xf) << 12)
117 #define FTGMAC100_DBLAC_TXDES_SIZE(x)	(((x) & 0xf) << 16)
118 #define FTGMAC100_DBLAC_IFG_CNT(x)	(((x) & 0x7) << 20)
119 #define FTGMAC100_DBLAC_IFG_INC		(1 << 23)
120 
121 /*
122  * DMA FIFO status register
123  */
124 #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos)	((dmafifos) & 0xf)
125 #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos)	(((dmafifos) >> 4) & 0xf)
126 #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos)	(((dmafifos) >> 8) & 0x7)
127 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos)	(((dmafifos) >> 12) & 0xf)
128 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos)	(((dmafifos) >> 16) & 0x3)
129 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos)	(((dmafifos) >> 18) & 0xf)
130 #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY		(1 << 26)
131 #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY		(1 << 27)
132 #define FTGMAC100_DMAFIFOS_RXDMA_GRANT		(1 << 28)
133 #define FTGMAC100_DMAFIFOS_TXDMA_GRANT		(1 << 29)
134 #define FTGMAC100_DMAFIFOS_RXDMA_REQ		(1 << 30)
135 #define FTGMAC100_DMAFIFOS_TXDMA_REQ		(1 << 31)
136 
137 /*
138  * Feature Register
139  */
140 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE	BIT(31)
141 
142 /*
143  * Receive buffer size register
144  */
145 #define FTGMAC100_RBSR_SIZE(x)		((x) & 0x3fff)
146 
147 /*
148  * MAC control register
149  */
150 #define FTGMAC100_MACCR_TXDMA_EN	(1 << 0)
151 #define FTGMAC100_MACCR_RXDMA_EN	(1 << 1)
152 #define FTGMAC100_MACCR_TXMAC_EN	(1 << 2)
153 #define FTGMAC100_MACCR_RXMAC_EN	(1 << 3)
154 #define FTGMAC100_MACCR_RM_VLAN		(1 << 4)
155 #define FTGMAC100_MACCR_HPTXR_EN	(1 << 5)
156 #define FTGMAC100_MACCR_LOOP_EN		(1 << 6)
157 #define FTGMAC100_MACCR_ENRX_IN_HALFTX	(1 << 7)
158 #define FTGMAC100_MACCR_FULLDUP		(1 << 8)
159 #define FTGMAC100_MACCR_GIGA_MODE	(1 << 9)
160 #define FTGMAC100_MACCR_CRC_APD		(1 << 10)
161 #define FTGMAC100_MACCR_PHY_LINK_LEVEL	(1 << 11)
162 #define FTGMAC100_MACCR_RX_RUNT		(1 << 12)
163 #define FTGMAC100_MACCR_JUMBO_LF	(1 << 13)
164 #define FTGMAC100_MACCR_RX_ALL		(1 << 14)
165 #define FTGMAC100_MACCR_HT_MULTI_EN	(1 << 15)
166 #define FTGMAC100_MACCR_RX_MULTIPKT	(1 << 16)
167 #define FTGMAC100_MACCR_RX_BROADPKT	(1 << 17)
168 #define FTGMAC100_MACCR_DISCARD_CRCERR	(1 << 18)
169 #define FTGMAC100_MACCR_FAST_MODE	(1 << 19)
170 #define FTGMAC100_MACCR_SW_RST		(1 << 31)
171 
172 /*
173  * test mode control register
174  */
175 #define FTGMAC100_TM_RQ_TX_VALID_DIS (1 << 28)
176 #define FTGMAC100_TM_RQ_RR_IDLE_PREV (1 << 27)
177 #define FTGMAC100_TM_DEFAULT                                                   \
178 	(FTGMAC100_TM_RQ_TX_VALID_DIS | FTGMAC100_TM_RQ_RR_IDLE_PREV)
179 
180 /*
181  * PHY control register
182  */
183 #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK	0x3f
184 #define FTGMAC100_PHYCR_MDC_CYCTHR(x)	((x) & 0x3f)
185 #define FTGMAC100_PHYCR_PHYAD(x)	(((x) & 0x1f) << 16)
186 #define FTGMAC100_PHYCR_REGAD(x)	(((x) & 0x1f) << 21)
187 #define FTGMAC100_PHYCR_MIIRD		(1 << 26)
188 #define FTGMAC100_PHYCR_MIIWR		(1 << 27)
189 
190 /*
191  * PHY data register
192  */
193 #define FTGMAC100_PHYDATA_MIIWDATA(x)		((x) & 0xffff)
194 #define FTGMAC100_PHYDATA_MIIRDATA(phydata)	(((phydata) >> 16) & 0xffff)
195 
196 /*
197  * Flow control register
198  */
199 #define FTGMAC100_FCR_FC_EN		(1 << 0)
200 #define FTGMAC100_FCR_FCTHR_EN		(1 << 2)
201 #define FTGMAC100_FCR_PAUSE_TIME(x)	(((x) & 0xffff) << 16)
202 
203 /*
204  * Transmit descriptor, aligned to 16 bytes
205  */
206 struct ftgmac100_txdes {
207 	__le32	txdes0; /* Control & status bits */
208 	__le32	txdes1; /* Irq, checksum and vlan control */
209 	__le32	txdes2; /* Reserved */
210 	__le32	txdes3; /* DMA buffer address */
211 } __attribute__ ((aligned(16)));
212 
213 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)	((x) & 0x3fff)
214 #define FTGMAC100_TXDES0_CRC_ERR	(1 << 19)
215 #define FTGMAC100_TXDES0_LTS		(1 << 28)
216 #define FTGMAC100_TXDES0_FTS		(1 << 29)
217 #define FTGMAC100_TXDES0_TXDMA_OWN	(1 << 31)
218 
219 #define FTGMAC100_TXDES1_VLANTAG_CI(x)	((x) & 0xffff)
220 #define FTGMAC100_TXDES1_INS_VLANTAG	(1 << 16)
221 #define FTGMAC100_TXDES1_TCP_CHKSUM	(1 << 17)
222 #define FTGMAC100_TXDES1_UDP_CHKSUM	(1 << 18)
223 #define FTGMAC100_TXDES1_IP_CHKSUM	(1 << 19)
224 #define FTGMAC100_TXDES1_LLC		(1 << 22)
225 #define FTGMAC100_TXDES1_TX2FIC		(1 << 30)
226 #define FTGMAC100_TXDES1_TXIC		(1 << 31)
227 
228 /*
229  * Receive descriptor, aligned to 16 bytes
230  */
231 struct ftgmac100_rxdes {
232 	__le32	rxdes0; /* Control & status bits */
233 	__le32	rxdes1;	/* Checksum and vlan status */
234 	__le32	rxdes2; /* length/type on AST2500 */
235 	__le32	rxdes3;	/* DMA buffer address */
236 } __attribute__ ((aligned(16)));
237 
238 #define FTGMAC100_RXDES0_VDBC		0x3fff
239 #define FTGMAC100_RXDES0_MULTICAST	(1 << 16)
240 #define FTGMAC100_RXDES0_BROADCAST	(1 << 17)
241 #define FTGMAC100_RXDES0_RX_ERR		(1 << 18)
242 #define FTGMAC100_RXDES0_CRC_ERR	(1 << 19)
243 #define FTGMAC100_RXDES0_FTL		(1 << 20)
244 #define FTGMAC100_RXDES0_RUNT		(1 << 21)
245 #define FTGMAC100_RXDES0_RX_ODD_NB	(1 << 22)
246 #define FTGMAC100_RXDES0_FIFO_FULL	(1 << 23)
247 #define FTGMAC100_RXDES0_PAUSE_OPCODE	(1 << 24)
248 #define FTGMAC100_RXDES0_PAUSE_FRAME	(1 << 25)
249 #define FTGMAC100_RXDES0_LRS		(1 << 28)
250 #define FTGMAC100_RXDES0_FRS		(1 << 29)
251 #define FTGMAC100_RXDES0_RXPKT_RDY	(1 << 31)
252 
253 /* Errors we care about for dropping packets */
254 #define RXDES0_ANY_ERROR		( \
255 	FTGMAC100_RXDES0_RX_ERR		| \
256 	FTGMAC100_RXDES0_CRC_ERR	| \
257 	FTGMAC100_RXDES0_FTL		| \
258 	FTGMAC100_RXDES0_RUNT		| \
259 	FTGMAC100_RXDES0_RX_ODD_NB)
260 
261 #define FTGMAC100_RXDES1_VLANTAG_CI	0xffff
262 #define FTGMAC100_RXDES1_PROT_MASK	(0x3 << 20)
263 #define FTGMAC100_RXDES1_PROT_NONIP	(0x0 << 20)
264 #define FTGMAC100_RXDES1_PROT_IP	(0x1 << 20)
265 #define FTGMAC100_RXDES1_PROT_TCPIP	(0x2 << 20)
266 #define FTGMAC100_RXDES1_PROT_UDPIP	(0x3 << 20)
267 #define FTGMAC100_RXDES1_LLC		(1 << 22)
268 #define FTGMAC100_RXDES1_DF		(1 << 23)
269 #define FTGMAC100_RXDES1_VLANTAG_AVAIL	(1 << 24)
270 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR	(1 << 25)
271 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR	(1 << 26)
272 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR	(1 << 27)
273 
274 #endif /* __FTGMAC100_H */
275