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Searched refs:FSL_SRDSCR1_OFFS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c28 #define FSL_SRDSCR1_OFFS 0x4 macro
122 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
125 out_be32(sd + FSL_SRDSCR1_OFFS, tmp); in fsl_serdes_init()
148 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
151 out_be32(sd + FSL_SRDSCR1_OFFS, tmp); in fsl_serdes_init()
172 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
175 out_be32(sd + FSL_SRDSCR1_OFFS, tmp); in fsl_serdes_init()
198 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
201 out_be32(sd + FSL_SRDSCR1_OFFS, tmp); in fsl_serdes_init()
215 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c25 #define FSL_SRDSCR1_OFFS 0x4 macro
82 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
84 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()
105 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
107 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()
127 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
129 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); in fsl_setup_serdes()