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Searched refs:FSL_SRDSCR0_TXEQA_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c20 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000 macro
116 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
144 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
166 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
194 tmp &= ~FSL_SRDSCR0_TXEQA_MASK; in fsl_serdes_init()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000 macro
78 FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK, in fsl_setup_serdes()