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Searched refs:FSL_SRDSCR0_OFFS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c19 #define FSL_SRDSCR0_OFFS 0x0 macro
115 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
120 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
143 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
146 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
165 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
170 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
193 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
196 out_be32(sd + FSL_SRDSCR0_OFFS, tmp); in fsl_serdes_init()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c19 #define FSL_SRDSCR0_OFFS 0x0 macro
55 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
57 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); in fsl_setup_serdes()
77 clrsetbits_be32(regs + FSL_SRDSCR0_OFFS, in fsl_setup_serdes()