xref: /openbmc/qemu/include/hw/arm/fsl-imx6ul.h (revision b0d1021e)
1 /*
2  * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
3  *
4  * i.MX6ul SoC definitions
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef FSL_IMX6UL_H
18 #define FSL_IMX6UL_H
19 
20 #include "hw/cpu/a15mpcore.h"
21 #include "hw/misc/imx6ul_ccm.h"
22 #include "hw/misc/imx6_src.h"
23 #include "hw/misc/imx7_snvs.h"
24 #include "hw/intc/imx_gpcv2.h"
25 #include "hw/watchdog/wdt_imx2.h"
26 #include "hw/gpio/imx_gpio.h"
27 #include "hw/char/imx_serial.h"
28 #include "hw/timer/imx_gpt.h"
29 #include "hw/timer/imx_epit.h"
30 #include "hw/i2c/imx_i2c.h"
31 #include "hw/sd/sdhci.h"
32 #include "hw/ssi/imx_spi.h"
33 #include "hw/net/imx_fec.h"
34 #include "hw/usb/chipidea.h"
35 #include "hw/usb/imx-usb-phy.h"
36 #include "exec/memory.h"
37 #include "cpu.h"
38 #include "qom/object.h"
39 #include "qemu/units.h"
40 
41 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
42 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
43 
44 enum FslIMX6ULConfiguration {
45     FSL_IMX6UL_NUM_CPUS         = 1,
46     FSL_IMX6UL_NUM_UARTS        = 8,
47     FSL_IMX6UL_NUM_ETHS         = 2,
48     FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
49     FSL_IMX6UL_NUM_USDHCS       = 2,
50     FSL_IMX6UL_NUM_WDTS         = 3,
51     FSL_IMX6UL_NUM_GPTS         = 2,
52     FSL_IMX6UL_NUM_EPITS        = 2,
53     FSL_IMX6UL_NUM_IOMUXCS      = 2,
54     FSL_IMX6UL_NUM_GPIOS        = 5,
55     FSL_IMX6UL_NUM_I2CS         = 4,
56     FSL_IMX6UL_NUM_ECSPIS       = 4,
57     FSL_IMX6UL_NUM_ADCS         = 2,
58     FSL_IMX6UL_NUM_USB_PHYS     = 2,
59     FSL_IMX6UL_NUM_USBS         = 2,
60     FSL_IMX6UL_NUM_SAIS         = 3,
61     FSL_IMX6UL_NUM_CANS         = 2,
62     FSL_IMX6UL_NUM_PWMS         = 8,
63 };
64 
65 struct FslIMX6ULState {
66     /*< private >*/
67     DeviceState    parent_obj;
68 
69     /*< public >*/
70     ARMCPU             cpu;
71     A15MPPrivState     a7mpcore;
72     IMXGPTState        gpt[FSL_IMX6UL_NUM_GPTS];
73     IMXEPITState       epit[FSL_IMX6UL_NUM_EPITS];
74     IMXGPIOState       gpio[FSL_IMX6UL_NUM_GPIOS];
75     IMX6ULCCMState     ccm;
76     IMX6SRCState       src;
77     IMX7SNVSState      snvs;
78     IMXGPCv2State      gpcv2;
79     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
80     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
81     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
82     IMXFECState        eth[FSL_IMX6UL_NUM_ETHS];
83     SDHCIState         usdhc[FSL_IMX6UL_NUM_USDHCS];
84     IMX2WdtState       wdt[FSL_IMX6UL_NUM_WDTS];
85     IMXUSBPHYState     usbphy[FSL_IMX6UL_NUM_USB_PHYS];
86     ChipideaState      usb[FSL_IMX6UL_NUM_USBS];
87     MemoryRegion       rom;
88     MemoryRegion       caam;
89     MemoryRegion       ocram;
90     MemoryRegion       ocram_alias;
91 
92     uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
93     bool               phy_connected[FSL_IMX6UL_NUM_ETHS];
94 };
95 
96 enum FslIMX6ULMemoryMap {
97     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
98     FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
99 
100     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
101     FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
102 
103     FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
104     FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
105 
106     FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
107     FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
108 
109     FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
110     FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
111 
112     FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
113     FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
114 
115     /* AIPS-2 Begin */
116     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
117 
118     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
119 
120     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
121     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
122     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
123     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
124 
125     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
126 
127     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
128     FSL_IMX6UL_QSPI_SIZE            = 0x500,
129 
130     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
131     FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
132 
133     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
134     FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
135 
136     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
137     FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
138 
139     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
140     FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
141 
142     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
143     FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
144 
145     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
146     FSL_IMX6UL_LCDIF_SIZE           = 0x100,
147 
148     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
149     FSL_IMX6UL_CSI_SIZE             = 0x100,
150 
151     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
152     FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
153 
154     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
155     FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
156 
157     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
158     FSL_IMX6UL_EIM_SIZE             = 0x100,
159 
160     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
161 
162     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
163     FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
164 
165     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
166     FSL_IMX6UL_ROMCP_SIZE           = 0x300,
167 
168     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
169     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
170     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
171 
172     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
173     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
174     FSL_IMX6UL_ADCn_SIZE            = 0x100,
175 
176     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
177     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
178 
179     FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
180     FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
181 
182     FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
183 
184     FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
185     FSL_IMX6UL_USBO2_USBMISC_SIZE   = 0x200,
186 
187     FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
188     FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
189 
190     FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
191     FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
192 
193     FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
194     FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
195 
196     FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
197     FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
198 
199     FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
200     FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
201     /* AIPS-2 End */
202 
203     /* AIPS-1 Begin */
204     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
205     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
206     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
207     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
208 
209     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
210     FSL_IMX6UL_SDMA_SIZE            = 0x300,
211 
212     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
213 
214     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
215     FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
216 
217     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
218     FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
219 
220     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
221 
222     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
223 
224     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
225     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
226 
227     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
228 
229     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
230     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
231 
232     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
233     FSL_IMX6UL_ANALOG_SIZE          = 0x300,
234 
235     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
236 
237     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
238     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
239 
240     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
241     FSL_IMX6UL_KPP_SIZE             = 0x10,
242 
243     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
244 
245     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
246     FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
247 
248     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
249     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
250     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
251     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
252     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
253 
254     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
255 
256     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
257     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
258     FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
259 
260     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
261     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
262     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
263     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
264     FSL_IMX6UL_PWMn_SIZE            = 0x20,
265 
266     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
267     FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
268 
269     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
270     FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
271 
272     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
273     FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
274 
275     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
276     FSL_IMX6UL_SPBA_SIZE            = 0x100,
277 
278     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
279     FSL_IMX6UL_ASRC_SIZE            = 0x100,
280 
281     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
282     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
283     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
284     FSL_IMX6UL_SAIn_SIZE            = 0x200,
285 
286     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
287     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
288     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
289 
290     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
291     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
292     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
293     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
294 
295     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
296     FSL_IMX6UL_SPDIF_SIZE           = 0x100,
297     /* AIPS-1 End */
298 
299     FSL_IMX6UL_BCH_ADDR             = 0x01808000,
300     FSL_IMX6UL_BCH_SIZE             = 0x200,
301 
302     FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
303     FSL_IMX6UL_GPMI_SIZE            = 0x200,
304 
305     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
306     FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
307 
308     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
309 
310     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
311     FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
312 
313     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
314     FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
315 
316     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
317     FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
318 
319     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
320     FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
321 };
322 
323 enum FslIMX6ULIRQs {
324     FSL_IMX6UL_IOMUXC_IRQ   = 0,
325     FSL_IMX6UL_DAP_IRQ      = 1,
326     FSL_IMX6UL_SDMA_IRQ     = 2,
327     FSL_IMX6UL_TSC_IRQ      = 3,
328     FSL_IMX6UL_SNVS_IRQ     = 4,
329     FSL_IMX6UL_LCDIF_IRQ    = 5,
330     FSL_IMX6UL_BEE_IRQ      = 6,
331     FSL_IMX6UL_CSI_IRQ      = 7,
332     FSL_IMX6UL_PXP_IRQ      = 8,
333     FSL_IMX6UL_SCTR1_IRQ    = 9,
334     FSL_IMX6UL_SCTR2_IRQ    = 10,
335     FSL_IMX6UL_WDOG3_IRQ    = 11,
336     FSL_IMX6UL_APBH_DMA_IRQ = 13,
337     FSL_IMX6UL_WEIM_IRQ     = 14,
338     FSL_IMX6UL_RAWNAND1_IRQ = 15,
339     FSL_IMX6UL_RAWNAND2_IRQ = 16,
340     FSL_IMX6UL_UART6_IRQ    = 17,
341     FSL_IMX6UL_SRTC_IRQ     = 19,
342     FSL_IMX6UL_SRTC_SEC_IRQ = 20,
343     FSL_IMX6UL_CSU_IRQ      = 21,
344     FSL_IMX6UL_USDHC1_IRQ   = 22,
345     FSL_IMX6UL_USDHC2_IRQ   = 23,
346     FSL_IMX6UL_SAI3_IRQ     = 24,
347     FSL_IMX6UL_SAI32_IRQ    = 25,
348 
349     FSL_IMX6UL_UART1_IRQ    = 26,
350     FSL_IMX6UL_UART2_IRQ    = 27,
351     FSL_IMX6UL_UART3_IRQ    = 28,
352     FSL_IMX6UL_UART4_IRQ    = 29,
353     FSL_IMX6UL_UART5_IRQ    = 30,
354 
355     FSL_IMX6UL_ECSPI1_IRQ   = 31,
356     FSL_IMX6UL_ECSPI2_IRQ   = 32,
357     FSL_IMX6UL_ECSPI3_IRQ   = 33,
358     FSL_IMX6UL_ECSPI4_IRQ   = 34,
359 
360     FSL_IMX6UL_I2C4_IRQ     = 35,
361     FSL_IMX6UL_I2C1_IRQ     = 36,
362     FSL_IMX6UL_I2C2_IRQ     = 37,
363     FSL_IMX6UL_I2C3_IRQ     = 38,
364 
365     FSL_IMX6UL_UART7_IRQ    = 39,
366     FSL_IMX6UL_UART8_IRQ    = 40,
367 
368     FSL_IMX6UL_USB1_IRQ     = 43,
369     FSL_IMX6UL_USB2_IRQ     = 42,
370     FSL_IMX6UL_USB_PHY1_IRQ = 44,
371     FSL_IMX6UL_USB_PHY2_IRQ = 45,
372 
373     FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
374     FSL_IMX6UL_CAAM_ERR_IRQ = 47,
375     FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
376     FSL_IMX6UL_TEMP_IRQ     = 49,
377     FSL_IMX6UL_ASRC_IRQ     = 50,
378     FSL_IMX6UL_SPDIF_IRQ    = 52,
379     FSL_IMX6UL_PMU_REG_IRQ  = 54,
380     FSL_IMX6UL_GPT1_IRQ     = 55,
381 
382     FSL_IMX6UL_EPIT1_IRQ    = 56,
383     FSL_IMX6UL_EPIT2_IRQ    = 57,
384 
385     FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
386     FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
387     FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
388     FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
389     FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
390     FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
391     FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
392     FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
393     FSL_IMX6UL_GPIO1_LOW_IRQ  = 66,
394     FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
395     FSL_IMX6UL_GPIO2_LOW_IRQ  = 68,
396     FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
397     FSL_IMX6UL_GPIO3_LOW_IRQ  = 70,
398     FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
399     FSL_IMX6UL_GPIO4_LOW_IRQ  = 72,
400     FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
401     FSL_IMX6UL_GPIO5_LOW_IRQ  = 74,
402     FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
403 
404     FSL_IMX6UL_WDOG1_IRQ    = 80,
405     FSL_IMX6UL_WDOG2_IRQ    = 81,
406 
407     FSL_IMX6UL_KPP_IRQ      = 82,
408 
409     FSL_IMX6UL_PWM1_IRQ     = 83,
410     FSL_IMX6UL_PWM2_IRQ     = 84,
411     FSL_IMX6UL_PWM3_IRQ     = 85,
412     FSL_IMX6UL_PWM4_IRQ     = 86,
413 
414     FSL_IMX6UL_CCM1_IRQ     = 87,
415     FSL_IMX6UL_CCM2_IRQ     = 88,
416 
417     FSL_IMX6UL_GPC_IRQ      = 89,
418 
419     FSL_IMX6UL_SRC_IRQ      = 91,
420 
421     FSL_IMX6UL_CPU_PERF_IRQ = 94,
422     FSL_IMX6UL_CPU_CTI_IRQ  = 95,
423 
424     FSL_IMX6UL_SRC_WDOG_IRQ = 96,
425 
426     FSL_IMX6UL_SAI1_IRQ     = 97,
427     FSL_IMX6UL_SAI2_IRQ     = 98,
428 
429     FSL_IMX6UL_ADC1_IRQ     = 100,
430     FSL_IMX6UL_ADC2_IRQ     = 101,
431 
432     FSL_IMX6UL_SJC_IRQ      = 104,
433 
434     FSL_IMX6UL_CAAM_RING0_IRQ = 105,
435     FSL_IMX6UL_CAAM_RING1_IRQ = 106,
436 
437     FSL_IMX6UL_QSPI_IRQ     = 107,
438 
439     FSL_IMX6UL_TZASC_IRQ    = 108,
440 
441     FSL_IMX6UL_GPT2_IRQ     = 109,
442 
443     FSL_IMX6UL_CAN1_IRQ     = 110,
444     FSL_IMX6UL_CAN2_IRQ     = 111,
445 
446     FSL_IMX6UL_SIM1_IRQ     = 112,
447     FSL_IMX6UL_SIM2_IRQ     = 113,
448 
449     FSL_IMX6UL_PWM5_IRQ     = 114,
450     FSL_IMX6UL_PWM6_IRQ     = 115,
451     FSL_IMX6UL_PWM7_IRQ     = 116,
452     FSL_IMX6UL_PWM8_IRQ     = 117,
453 
454     FSL_IMX6UL_ENET1_IRQ    = 118,
455     FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
456     FSL_IMX6UL_ENET2_IRQ    = 120,
457     FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
458 
459     FSL_IMX6UL_PMU_CORE_IRQ = 127,
460     FSL_IMX6UL_MAX_IRQ      = 128,
461 };
462 
463 #endif /* FSL_IMX6UL_H */
464