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Searched refs:FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c54 cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
186 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()
367 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()
415 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, in fsl_serdes_init()
/openbmc/u-boot/board/freescale/ls1046aqds/
H A Deth.c281 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in board_eth_init()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h284 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff macro