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Searched refs:FPCR_FZ (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dvfp_helper.c138 if ((env->vfp.fpcr & (FPCR_FZ | FPCR_AH)) != FPCR_FZ) { in vfp_get_fpsr_from_host()
215 if (changed & FPCR_FZ) { in vfp_set_fpcr_to_host()
216 bool ftz_enabled = val & FPCR_FZ; in vfp_set_fpcr_to_host()
223 if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) { in vfp_set_fpcr_to_host()
229 (val & (FPCR_FZ | FPCR_AH)) == FPCR_FZ; in vfp_set_fpcr_to_host()
263 if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) { in vfp_set_fpcr_to_host()
/openbmc/qemu/target/arm/
H A Dvfp_fpscr.c140 val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16 | in vfp_set_fpcr_masked()
H A Dcpu.h1751 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ macro
1786 FPCR_FZ | FPCR_DN | FPCR_AHP)
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c2125 uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; in nvic_writel()