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Searched refs:FIELD_PREP (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c61 #define MAC_DEF_DELAY_1G FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 16) | \
62 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 10) | \
63 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 16) | \
64 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 10)
65 #define MAC_DEF_DELAY_100M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \
66 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \
67 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) | \
68 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16)
69 #define MAC_DEF_DELAY_10M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \
70 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \
[all …]
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c366 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); in meson_saradc_enable_channel()
371 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel); in meson_saradc_enable_channel()
375 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, in meson_saradc_enable_channel()
381 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, in meson_saradc_enable_channel()
450 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); in meson_saradc_set_chan7_mux()
535 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, in meson_saradc_init()
539 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, in meson_saradc_init()
545 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, in meson_saradc_init()
549 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, in meson_saradc_init()
556 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); in meson_saradc_init()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c44 tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, in uniphier_ld20_sscpll_init()
51 tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, in uniphier_ld20_sscpll_init()
97 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); in uniphier_ld20_sscpll_set_regi()
/openbmc/u-boot/drivers/mmc/
H A Dsdhci-cadence.c93 tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | in sdhci_cdns_write_phy_reg()
94 FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); in sdhci_cdns_write_phy_reg()
160 tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); in sdhci_cdns_set_control_reg()
179 tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); in sdhci_cdns_set_tune_val()
/openbmc/u-boot/drivers/net/
H A Dmt7628-eth.c184 FIELD_PREP(PCR0_PHY_REG, phy_register) | in mii_mgr_read()
185 FIELD_PREP(PCR0_PHY_ADDR, phy_addr), in mii_mgr_read()
211 data = FIELD_PREP(PCR0_WT_DATA, write_data) | in mii_mgr_write()
212 FIELD_PREP(PCR0_PHY_REG, phy_register) | in mii_mgr_write()
213 FIELD_PREP(PCR0_PHY_ADDR, phy_addr) | in mii_mgr_write()
397 priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length); in mt7628_eth_send()
486 priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1); in mt7628_eth_start()
/openbmc/u-boot/drivers/phy/
H A Dmeson-gxl-usb3.c121 val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff); in phy_meson_gxl_usb3_power_on()
149 val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20); in phy_meson_gxl_usb3_init()
/openbmc/u-boot/include/linux/
H A Dbitfield.h86 #define FIELD_PREP(_mask, _val) \ macro
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddenali.c980 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); in denali_setup_data_interface()
989 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); in denali_setup_data_interface()
998 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); in denali_setup_data_interface()
1012 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); in denali_setup_data_interface()
1027 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); in denali_setup_data_interface()
1037 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); in denali_setup_data_interface()
1050 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); in denali_setup_data_interface()
1061 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); in denali_setup_data_interface()
1309 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | in denali_init()
1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), in denali_init()
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0046-Corstone1000-Change-MMCOMM-buffer-location.patch36 #define PREP_SEPROXY_EVT(x) (FIELD_PREP(PREP_SEPROXY_EVT_MASK, (x)))
H A D0011-efi-corstone1000-fwu-introduce-EFI-capsule-update.patch84 +#define PREP_SEPROXY_SVC_ID(x) (FIELD_PREP(PREP_SEPROXY_SVC_ID_MASK, (x)))
87 +#define PREP_SEPROXY_EVT(x) (FIELD_PREP(PREP_SEPROXY_EVT_MASK, (x)))
H A D0004-FF-A-v15-arm_ffa-introduce-Arm-FF-A-support.patch1947 + (FIELD_PREP(MAJOR_VERSION_MASK, (major)) | \
1948 + FIELD_PREP(MINOR_VERSION_MASK, (minor)))
1963 + (FIELD_PREP(PREP_SELF_ENDPOINT_ID_MASK, (x)))
1969 + (FIELD_PREP(PREP_PART_ENDPOINT_ID_MASK, (x)))
H A D0006-FF-A-v15-arm_ffa-introduce-sandbox-FF-A-support.patch215 + (FIELD_PREP(PREP_SRC_SP_ID_MASK, (x)))
220 + (FIELD_PREP(PREP_NS_PHYS_ENDPOINT_ID_MASK, (x)))
/openbmc/u-boot/drivers/misc/
H A Daspeed_dp.c146 writel(FIELD_PREP(MCU_INTR_CTRL_EN, 0xff), MCU_INTR_CTRL); in aspeed_dp_probe()
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2600.c814 reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | in ast2600_sdrammc_common_init()
815 FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); in ast2600_sdrammc_common_init()