1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * FlexBus Internal Memory Map
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef __FLEXBUS_H
10 #define __FLEXBUS_H
11 
12 /*********************************************************************
13 * FlexBus Chip Selects (FBCS)
14 *********************************************************************/
15 #ifdef CONFIG_M5235
16 typedef struct fbcs {
17     u16 csar0;      /* Chip-select Address */
18     u16 res1;
19     u32 csmr0;      /* Chip-select Mask */
20     u16 res2;
21     u16 cscr0;      /* Chip-select Control */
22 
23     u16 csar1;
24     u16 res3;
25     u32 csmr1;
26     u16 res4;
27     u16 cscr1;
28 
29     u16 csar2;
30     u16 res5;
31     u32 csmr2;
32     u16 res6;
33     u16 cscr2;
34 
35     u16 csar3;
36     u16 res7;
37     u32 csmr3;
38     u16 res8;
39     u16 cscr3;
40 
41     u16 csar4;
42     u16 res9;
43     u32 csmr4;
44     u16 res10;
45     u16 cscr4;
46 
47     u16 csar5;
48     u16 res11;
49     u32 csmr5;
50     u16 res12;
51     u16 cscr5;
52 
53     u16 csar6;
54     u16 res13;
55     u32 csmr6;
56     u16 res14;
57     u16 cscr6;
58 
59     u16 csar7;
60     u16 res15;
61     u32 csmr7;
62     u16 res16;
63     u16 cscr7;
64 } fbcs_t;
65 #else
66 typedef struct fbcs {
67 	u32 csar0;		/* Chip-select Address */
68 	u32 csmr0;		/* Chip-select Mask */
69 	u32 cscr0;		/* Chip-select Control */
70 	u32 csar1;
71 	u32 csmr1;
72 	u32 cscr1;
73 	u32 csar2;
74 	u32 csmr2;
75 	u32 cscr2;
76 	u32 csar3;
77 	u32 csmr3;
78 	u32 cscr3;
79 	u32 csar4;
80 	u32 csmr4;
81 	u32 cscr4;
82 	u32 csar5;
83 	u32 csmr5;
84 	u32 cscr5;
85 	u32 csar6;
86 	u32 csmr6;
87 	u32 cscr6;
88 	u32 csar7;
89 	u32 csmr7;
90 	u32 cscr7;
91 } fbcs_t;
92 #endif
93 
94 #define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
95 
96 #define FBCS_CSMR_BAM(x)		(((x) & 0xFFFF) << 16)
97 #define FBCS_CSMR_BAM_MASK		(0x0000FFFF)
98 #define FBCS_CSMR_BAM_4G		(0xFFFF0000)
99 #define FBCS_CSMR_BAM_2G		(0x7FFF0000)
100 #define FBCS_CSMR_BAM_1G		(0x3FFF0000)
101 #define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
102 #define FBCS_CSMR_BAM_512M		(0x1FFF0000)
103 #define FBCS_CSMR_BAM_256M		(0x0FFF0000)
104 #define FBCS_CSMR_BAM_128M		(0x07FF0000)
105 #define FBCS_CSMR_BAM_64M		(0x03FF0000)
106 #define FBCS_CSMR_BAM_32M		(0x01FF0000)
107 #define FBCS_CSMR_BAM_16M		(0x00FF0000)
108 #define FBCS_CSMR_BAM_8M		(0x007F0000)
109 #define FBCS_CSMR_BAM_4M		(0x003F0000)
110 #define FBCS_CSMR_BAM_2M		(0x001F0000)
111 #define FBCS_CSMR_BAM_1M		(0x000F0000)
112 #define FBCS_CSMR_BAM_1024K		(0x000F0000)
113 #define FBCS_CSMR_BAM_512K		(0x00070000)
114 #define FBCS_CSMR_BAM_256K		(0x00030000)
115 #define FBCS_CSMR_BAM_128K		(0x00010000)
116 #define FBCS_CSMR_BAM_64K		(0x00000000)
117 
118 #ifdef CONFIG_M5249
119 #define FBCS_CSMR_WP			(0x00000080)
120 #define FBCS_CSMR_AM			(0x00000040)
121 #define FBCS_CSMR_CI			(0x00000020)
122 #define FBCS_CSMR_SC			(0x00000010)
123 #define FBCS_CSMR_SD			(0x00000008)
124 #define FBCS_CSMR_UC			(0x00000004)
125 #define FBCS_CSMR_UD			(0x00000002)
126 #else
127 #define FBCS_CSMR_WP			(0x00000100)
128 #endif
129 #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
130 
131 #ifdef CONFIG_M5235
132 #define FBCS_CSCR_SRWS(x)       (((x) & 0x3) << 14)
133 #define FBCS_CSCR_IWS(x)        (((x) & 0xF) << 10)
134 #define FBCS_CSCR_AA_ON         (1 << 8)
135 #define FBCS_CSCR_AA_OFF        (0 << 8)
136 #define FBCS_CSCR_PS_32         (0 << 6)
137 #define FBCS_CSCR_PS_16         (2 << 6)
138 #define FBCS_CSCR_PS_8          (1 << 6)
139 #define FBCS_CSCR_BEM_ON        (1 << 5)
140 #define FBCS_CSCR_BEM_OFF       (0 << 5)
141 #define FBCS_CSCR_BSTR_ON       (1 << 4)
142 #define FBCS_CSCR_BSTR_OFF      (0 << 4)
143 #define FBCS_CSCR_BSTW_ON       (1 << 3)
144 #define FBCS_CSCR_BSTW_OFF      (0 << 3)
145 #define FBCS_CSCR_SWWS(x)       (((x) & 0x7) << 0)
146 #else
147 #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
148 #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
149 #define FBCS_CSCR_SWSEN			(0x00800000)
150 #define FBCS_CSCR_ASET(x)		(((x) & 0x03) << 20)
151 #define FBCS_CSCR_ASET_MASK		(0xFFCFFFFF)
152 #define FBCS_CSCR_RDAH(x)		(((x) & 0x03) << 18)
153 #define FBCS_CSCR_RDAH_MASK		(0xFFF3FFFF)
154 #define FBCS_CSCR_WRAH(x)		(((x) & 0x03) << 16)
155 #define FBCS_CSCR_WRAH_MASK		(0xFFFCFFFF)
156 #define FBCS_CSCR_WS(x)			(((x) & 0x3F) << 10)
157 #define FBCS_CSCR_WS_MASK		(0xFFFF03FF)
158 #define FBCS_CSCR_SBM			(0x00000200)
159 #define FBCS_CSCR_AA			(0x00000100)
160 #define FBCS_CSCR_PS(x)			(((x) & 0x03) << 6)
161 #define FBCS_CSCR_PS_MASK		(0xFFFFFF3F)
162 #define FBCS_CSCR_BEM			(0x00000020)
163 #define FBCS_CSCR_BSTR			(0x00000010)
164 #define FBCS_CSCR_BSTW			(0x00000008)
165 
166 #define FBCS_CSCR_PS_16			(0x00000080)
167 #define FBCS_CSCR_PS_8			(0x00000040)
168 #define FBCS_CSCR_PS_32			(0x00000000)
169 #endif
170 
171 #endif				/* __FLEXBUS_H */
172