Searched refs:EXYNOS5_DREXI_TIMINGROW1 (Results 1 – 1 of 1) sorted by relevance
33 #define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) macro390 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()392 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()