Searched refs:EXYNOS5_DREXI_TIMINGAREF (Results 1 – 1 of 1) sorted by relevance
29 #define EXYNOS5_DREXI_TIMINGAREF (0x0030) macro387 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_set_bypass_dram_timings()427 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_dram_change_timings()