Searched refs:ET0_GTX_CLK_A (Results 1 – 2 of 2) sorted by relevance
35 #define ET0_GTX_CLK_A (0x4 << 6) macro44 (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
817 PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),1445 GPIO_FN(ET0_GTX_CLK_A),