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Searched refs:ESUB_CLK_BASE_ADDR (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-eth.c13 #define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
16 #define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
18 #define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
22 #define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
25 #define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
32 #define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
H A Dclk-bcm235xx.c312 .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-eth.c13 #define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
16 #define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
18 #define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
22 #define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
25 #define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
32 #define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
H A Dclk-bcm281xx.c316 .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
/openbmc/u-boot/arch/arm/include/asm/arch-bcm281xx/
H A Dsysmap.h12 #define ESUB_CLK_BASE_ADDR 0x38000000 macro