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Searched refs:ESDCTL_DDR2_CONFIG (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/CarMediaLab/flea3/
H A Dflea3.c31 #define ESDCTL_DDR2_CONFIG 0x007FFC3F macro
60 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, in board_setup_sdram()
/openbmc/u-boot/board/woodburn/
H A Dwoodburn.c29 #define ESDCTL_DDR2_CONFIG 0x007FFC3F macro
53 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, in board_setup_sdram()
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dmx35pdk.h32 #define ESDCTL_DDR2_CONFIG 0x007FFC3F macro
H A Dlowlevel_init.S162 ldreq r3, =ESDCTL_DDR2_CONFIG