Searched refs:EN0 (Results 1 – 4 of 4) sorted by relevance
299 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()301 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()303 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()305 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()307 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()309 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()311 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()313 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()315 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()317 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()[all …]
22 #define EN0 0x04 macro
25 #define EN0 0 /* MODE == encrypt */ macro
40 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.79 hardware input to PMIC i.e. EN0, EN1 or85 for hardware input pin EN0.