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Searched refs:DWB_OGAM_RAMA_REGION_0_1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb.h86 SR(DWB_OGAM_RAMA_REGION_0_1),\
247 SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
248 SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
249 SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
250 SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
791 uint32_t DWB_OGAM_RAMA_REGION_0_1; member
H A Ddcn30_dwb_cm.c107 gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1); in dwb3_program_ogam_luta_settings()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h636 SR_ARR(DWB_OGAM_RAMA_REGION_0_1, id), \