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Searched refs:DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h9466 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h19879 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h18711 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h14309 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_1_0_sh_mask.h17659 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h20735 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h18748 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h21489 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h20706 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h28115 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h21753 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h21779 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h14306 #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT … macro