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Searched refs:DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h23095 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h38452 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h45216 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h42645 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h47409 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h45690 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h49036 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h44479 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h49748 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h51112 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h51783 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h42597 #define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro