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Searched refs:DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h22484 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h37834 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h44594 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h42168 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h46791 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h45072 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h48418 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h43868 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h49130 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h50501 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h51161 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h42120 #define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT … macro