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Searched refs:DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h22572 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h37922 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h44682 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h42256 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h46879 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h45160 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h48506 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h43956 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h49218 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h50589 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h51249 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h42208 #define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT … macro