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Searched refs:DRCMR0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/dma/
H A Dpxa2xx_dma.c72 #define DRCMR0 0x0100 /* Request to Channel Map register 0 */ macro
280 offset -= DRCMR64 - DRCMR0 - (64 << 2); in pxa2xx_dma_read()
282 case DRCMR0 ... DRCMR63: in pxa2xx_dma_read()
283 channel = (offset - DRCMR0) >> 2; in pxa2xx_dma_read()
340 offset -= DRCMR64 - DRCMR0 - (64 << 2); in pxa2xx_dma_write()
342 case DRCMR0 ... DRCMR63: in pxa2xx_dma_write()
343 channel = (offset - DRCMR0) >> 2; in pxa2xx_dma_write()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h155 #define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */ macro