Home
last modified time | relevance | path

Searched refs:DRAMTIMING0_CFG_TCL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c280 io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR + in sdram_mmr_init_full()
306 ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + in sdram_mmr_init_full()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_s10.h124 #define DRAMTIMING0_CFG_TCL(x) \ macro