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Searched refs:DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_sh_mask.h23272 #define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT … macro
H A Ddpcs_4_2_0_sh_mask.h32627 #define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT … macro
H A Ddpcs_4_2_2_sh_mask.h32781 #define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT … macro
H A Ddpcs_4_2_3_sh_mask.h31200 #define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT … macro