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Searched refs:DPCD_LANE0_1_STATUS (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/include/hw/display/
H A Ddpcd.h81 #define DPCD_LANE0_1_STATUS 0x202 macro
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.h85 #define DPCD_LANE0_1_STATUS 0x202 macro
H A Dhandlers.c1128 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; in dp_aux_ch_ctl_link_training()
1135 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; in dp_aux_ch_ctl_link_training()
1136 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; in dp_aux_ch_ctl_link_training()
/openbmc/qemu/hw/display/
H A Ddpcd.c109 s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE in dpcd_reset()
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_edp.c343 return link_status[r - DPCD_LANE0_1_STATUS]; in edp_link_status()
349 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status, in rk_edp_dpcd_read_link_status()
355 int i = DPCD_LANE0_1_STATUS + (lane >> 1); in edp_get_lane_status()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h486 #define DPCD_LANE0_1_STATUS (0x0202) macro
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h624 #define DPCD_LANE0_1_STATUS (0x0202) macro
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp.c395 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2, in exynos_dp_read_dpcd_lane_stat()