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Searched refs:DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h17931 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_0_3_sh_mask.h18804 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_0_1_sh_mask.h30022 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_2_1_0_sh_mask.h36458 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_2_1_sh_mask.h28174 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_1_0_sh_mask.h31243 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_1_2_sh_mask.h33269 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_1_5_sh_mask.h31137 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_1_6_sh_mask.h34037 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_0_2_sh_mask.h34666 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_1_4_sh_mask.h38725 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_0_0_sh_mask.h39459 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_2_0_0_sh_mask.h40410 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
H A Ddcn_3_2_0_sh_mask.h28171 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h38136 #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT macro