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Searched refs:DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h18147 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h19053 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h30271 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h36707 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h28448 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_1_0_sh_mask.h31472 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h33518 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h31434 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h34334 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h34915 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h38975 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h39708 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h40659 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h28445 #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT … macro