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Searched refs:DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h17950 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_0_3_sh_mask.h18823 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_2_1_0_sh_mask.h36477 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_1_0_sh_mask.h31261 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_0_1_sh_mask.h30041 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_2_1_sh_mask.h28193 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_1_2_sh_mask.h33288 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_1_5_sh_mask.h31156 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_1_6_sh_mask.h34056 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_1_4_sh_mask.h38744 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_0_2_sh_mask.h34685 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_2_0_0_sh_mask.h40429 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_0_0_sh_mask.h39478 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
H A Ddcn_3_2_0_sh_mask.h28190 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h38151 #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT macro