Home
last modified time | relevance | path

Searched refs:DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5965 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L macro
H A Ddce_8_0_sh_mask.h7743 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 macro
H A Ddce_10_0_sh_mask.h6787 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 macro
H A Ddce_11_0_sh_mask.h6683 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 macro
H A Ddce_11_2_sh_mask.h7763 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 macro
H A Ddce_12_0_sh_mask.h4699 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1377 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2320 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2175 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_1_0_sh_mask.h3669 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_2_sh_mask.h1800 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_5_sh_mask.h1311 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2367 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2246 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10430 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2313 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2443 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … macro