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Searched refs:DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5963 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L macro
H A Ddce_8_0_sh_mask.h7745 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 macro
H A Ddce_10_0_sh_mask.h6789 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 macro
H A Ddce_11_0_sh_mask.h6685 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 macro
H A Ddce_11_2_sh_mask.h7765 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 macro
H A Ddce_12_0_sh_mask.h4700 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1378 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2176 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_1_0_sh_mask.h3670 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2321 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_2_sh_mask.h1801 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_5_sh_mask.h1312 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2368 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10431 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2247 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2444 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2314 #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … macro