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Searched refs:DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5717 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L macro
H A Ddce_8_0_sh_mask.h7883 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 macro
H A Ddce_10_0_sh_mask.h6903 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 macro
H A Ddce_11_0_sh_mask.h6797 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 macro
H A Ddce_11_2_sh_mask.h7877 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 macro
H A Ddce_12_0_sh_mask.h4871 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1521 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2484 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2343 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_1_0_sh_mask.h3837 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_2_sh_mask.h1968 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2535 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2414 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10598 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2481 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2611 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … macro