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Searched refs:DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h2965 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h4330 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h4159 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_1_0_sh_mask.h5426 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h4090 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h4659 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h4297 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h12456 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h4401 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h4425 #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK … macro