xref: /openbmc/u-boot/drivers/net/designware.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5  */
6 
7 #ifndef _DW_ETH_H
8 #define _DW_ETH_H
9 
10 #ifdef CONFIG_DM_GPIO
11 #include <asm-generic/gpio.h>
12 #endif
13 
14 #define CONFIG_TX_DESCR_NUM	16
15 #define CONFIG_RX_DESCR_NUM	16
16 #define CONFIG_ETH_BUFSIZE	2048
17 #define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
18 #define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
19 
20 #define CONFIG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
21 #define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
22 
23 struct eth_mac_regs {
24 	u32 conf;		/* 0x00 */
25 	u32 framefilt;		/* 0x04 */
26 	u32 hashtablehigh;	/* 0x08 */
27 	u32 hashtablelow;	/* 0x0c */
28 	u32 miiaddr;		/* 0x10 */
29 	u32 miidata;		/* 0x14 */
30 	u32 flowcontrol;	/* 0x18 */
31 	u32 vlantag;		/* 0x1c */
32 	u32 version;		/* 0x20 */
33 	u8 reserved_1[20];
34 	u32 intreg;		/* 0x38 */
35 	u32 intmask;		/* 0x3c */
36 	u32 macaddr0hi;		/* 0x40 */
37 	u32 macaddr0lo;		/* 0x44 */
38 };
39 
40 /* MAC configuration register definitions */
41 #define FRAMEBURSTENABLE	(1 << 21)
42 #define MII_PORTSELECT		(1 << 15)
43 #define FES_100			(1 << 14)
44 #define DISABLERXOWN		(1 << 13)
45 #define FULLDPLXMODE		(1 << 11)
46 #define RXENABLE		(1 << 2)
47 #define TXENABLE		(1 << 3)
48 
49 /* MII address register definitions */
50 #define MII_BUSY		(1 << 0)
51 #define MII_WRITE		(1 << 1)
52 #define MII_CLKRANGE_60_100M	(0)
53 #define MII_CLKRANGE_100_150M	(0x4)
54 #define MII_CLKRANGE_20_35M	(0x8)
55 #define MII_CLKRANGE_35_60M	(0xC)
56 #define MII_CLKRANGE_150_250M	(0x10)
57 #define MII_CLKRANGE_250_300M	(0x14)
58 
59 #define MIIADDRSHIFT		(11)
60 #define MIIREGSHIFT		(6)
61 #define MII_REGMSK		(0x1F << 6)
62 #define MII_ADDRMSK		(0x1F << 11)
63 
64 
65 struct eth_dma_regs {
66 	u32 busmode;		/* 0x00 */
67 	u32 txpolldemand;	/* 0x04 */
68 	u32 rxpolldemand;	/* 0x08 */
69 	u32 rxdesclistaddr;	/* 0x0c */
70 	u32 txdesclistaddr;	/* 0x10 */
71 	u32 status;		/* 0x14 */
72 	u32 opmode;		/* 0x18 */
73 	u32 intenable;		/* 0x1c */
74 	u32 reserved1[2];
75 	u32 axibus;		/* 0x28 */
76 	u32 reserved2[7];
77 	u32 currhosttxdesc;	/* 0x48 */
78 	u32 currhostrxdesc;	/* 0x4c */
79 	u32 currhosttxbuffaddr;	/* 0x50 */
80 	u32 currhostrxbuffaddr;	/* 0x54 */
81 };
82 
83 #define DW_DMA_BASE_OFFSET	(0x1000)
84 
85 /* Default DMA Burst length */
86 #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
87 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
88 #endif
89 
90 /* Bus mode register definitions */
91 #define FIXEDBURST		(1 << 16)
92 #define PRIORXTX_41		(3 << 14)
93 #define PRIORXTX_31		(2 << 14)
94 #define PRIORXTX_21		(1 << 14)
95 #define PRIORXTX_11		(0 << 14)
96 #define DMA_PBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
97 #define RXHIGHPRIO		(1 << 1)
98 #define DMAMAC_SRST		(1 << 0)
99 
100 /* Poll demand definitions */
101 #define POLL_DATA		(0xFFFFFFFF)
102 
103 /* Operation mode definitions */
104 #define STOREFORWARD		(1 << 21)
105 #define FLUSHTXFIFO		(1 << 20)
106 #define TXSTART			(1 << 13)
107 #define TXSECONDFRAME		(1 << 2)
108 #define RXSTART			(1 << 1)
109 
110 /* Descriptior related definitions */
111 #define MAC_MAX_FRAME_SZ	(1600)
112 
113 struct dmamacdescr {
114 	u32 txrx_status;
115 	u32 dmamac_cntl;
116 	u32 dmamac_addr;
117 	u32 dmamac_next;
118 } __aligned(ARCH_DMA_MINALIGN);
119 
120 /*
121  * txrx_status definitions
122  */
123 
124 /* tx status bits definitions */
125 #if defined(CONFIG_DW_ALTDESCRIPTOR)
126 
127 #define DESC_TXSTS_OWNBYDMA		(1 << 31)
128 #define DESC_TXSTS_TXINT		(1 << 30)
129 #define DESC_TXSTS_TXLAST		(1 << 29)
130 #define DESC_TXSTS_TXFIRST		(1 << 28)
131 #define DESC_TXSTS_TXCRCDIS		(1 << 27)
132 
133 #define DESC_TXSTS_TXPADDIS		(1 << 26)
134 #define DESC_TXSTS_TXCHECKINSCTRL	(3 << 22)
135 #define DESC_TXSTS_TXRINGEND		(1 << 21)
136 #define DESC_TXSTS_TXCHAIN		(1 << 20)
137 #define DESC_TXSTS_MSK			(0x1FFFF << 0)
138 
139 #else
140 
141 #define DESC_TXSTS_OWNBYDMA		(1 << 31)
142 #define DESC_TXSTS_MSK			(0x1FFFF << 0)
143 
144 #endif
145 
146 /* rx status bits definitions */
147 #define DESC_RXSTS_OWNBYDMA		(1 << 31)
148 #define DESC_RXSTS_DAFILTERFAIL		(1 << 30)
149 #define DESC_RXSTS_FRMLENMSK		(0x3FFF << 16)
150 #define DESC_RXSTS_FRMLENSHFT		(16)
151 
152 #define DESC_RXSTS_ERROR		(1 << 15)
153 #define DESC_RXSTS_RXTRUNCATED		(1 << 14)
154 #define DESC_RXSTS_SAFILTERFAIL		(1 << 13)
155 #define DESC_RXSTS_RXIPC_GIANTFRAME	(1 << 12)
156 #define DESC_RXSTS_RXDAMAGED		(1 << 11)
157 #define DESC_RXSTS_RXVLANTAG		(1 << 10)
158 #define DESC_RXSTS_RXFIRST		(1 << 9)
159 #define DESC_RXSTS_RXLAST		(1 << 8)
160 #define DESC_RXSTS_RXIPC_GIANT		(1 << 7)
161 #define DESC_RXSTS_RXCOLLISION		(1 << 6)
162 #define DESC_RXSTS_RXFRAMEETHER		(1 << 5)
163 #define DESC_RXSTS_RXWATCHDOG		(1 << 4)
164 #define DESC_RXSTS_RXMIIERROR		(1 << 3)
165 #define DESC_RXSTS_RXDRIBBLING		(1 << 2)
166 #define DESC_RXSTS_RXCRC		(1 << 1)
167 
168 /*
169  * dmamac_cntl definitions
170  */
171 
172 /* tx control bits definitions */
173 #if defined(CONFIG_DW_ALTDESCRIPTOR)
174 
175 #define DESC_TXCTRL_SIZE1MASK		(0x1FFF << 0)
176 #define DESC_TXCTRL_SIZE1SHFT		(0)
177 #define DESC_TXCTRL_SIZE2MASK		(0x1FFF << 16)
178 #define DESC_TXCTRL_SIZE2SHFT		(16)
179 
180 #else
181 
182 #define DESC_TXCTRL_TXINT		(1 << 31)
183 #define DESC_TXCTRL_TXLAST		(1 << 30)
184 #define DESC_TXCTRL_TXFIRST		(1 << 29)
185 #define DESC_TXCTRL_TXCHECKINSCTRL	(3 << 27)
186 #define DESC_TXCTRL_TXCRCDIS		(1 << 26)
187 #define DESC_TXCTRL_TXRINGEND		(1 << 25)
188 #define DESC_TXCTRL_TXCHAIN		(1 << 24)
189 
190 #define DESC_TXCTRL_SIZE1MASK		(0x7FF << 0)
191 #define DESC_TXCTRL_SIZE1SHFT		(0)
192 #define DESC_TXCTRL_SIZE2MASK		(0x7FF << 11)
193 #define DESC_TXCTRL_SIZE2SHFT		(11)
194 
195 #endif
196 
197 /* rx control bits definitions */
198 #if defined(CONFIG_DW_ALTDESCRIPTOR)
199 
200 #define DESC_RXCTRL_RXINTDIS		(1 << 31)
201 #define DESC_RXCTRL_RXRINGEND		(1 << 15)
202 #define DESC_RXCTRL_RXCHAIN		(1 << 14)
203 
204 #define DESC_RXCTRL_SIZE1MASK		(0x1FFF << 0)
205 #define DESC_RXCTRL_SIZE1SHFT		(0)
206 #define DESC_RXCTRL_SIZE2MASK		(0x1FFF << 16)
207 #define DESC_RXCTRL_SIZE2SHFT		(16)
208 
209 #else
210 
211 #define DESC_RXCTRL_RXINTDIS		(1 << 31)
212 #define DESC_RXCTRL_RXRINGEND		(1 << 25)
213 #define DESC_RXCTRL_RXCHAIN		(1 << 24)
214 
215 #define DESC_RXCTRL_SIZE1MASK		(0x7FF << 0)
216 #define DESC_RXCTRL_SIZE1SHFT		(0)
217 #define DESC_RXCTRL_SIZE2MASK		(0x7FF << 11)
218 #define DESC_RXCTRL_SIZE2SHFT		(11)
219 
220 #endif
221 
222 struct dw_eth_dev {
223 	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
224 	struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
225 	char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
226 	char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
227 
228 	u32 interface;
229 	u32 max_speed;
230 	u32 tx_currdescnum;
231 	u32 rx_currdescnum;
232 
233 	struct eth_mac_regs *mac_regs_p;
234 	struct eth_dma_regs *dma_regs_p;
235 #ifndef CONFIG_DM_ETH
236 	struct eth_device *dev;
237 #endif
238 #ifdef CONFIG_DM_GPIO
239 	struct gpio_desc reset_gpio;
240 #endif
241 #ifdef CONFIG_CLK
242 	struct clk *clocks;	/* clock list */
243 	int clock_count;	/* number of clock in clock list */
244 #endif
245 
246 	struct phy_device *phydev;
247 	struct mii_dev *bus;
248 };
249 
250 #ifdef CONFIG_DM_ETH
251 int designware_eth_ofdata_to_platdata(struct udevice *dev);
252 int designware_eth_probe(struct udevice *dev);
253 extern const struct eth_ops designware_eth_ops;
254 
255 struct dw_eth_pdata {
256 	struct eth_pdata eth_pdata;
257 	u32 reset_delays[3];
258 };
259 
260 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
261 int designware_eth_enable(struct dw_eth_dev *priv);
262 int designware_eth_send(struct udevice *dev, void *packet, int length);
263 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
264 int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
265 				   int length);
266 void designware_eth_stop(struct udevice *dev);
267 int designware_eth_write_hwaddr(struct udevice *dev);
268 #endif
269 
270 #endif
271