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Searched refs:DEF_INT_MASK (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/net/ethernet/hisilicon/
H A Dhisi_femac.c72 #define DEF_INT_MASK (IRQ_INT_MULTI_RXRDY | \ macro
316 writel(ints & DEF_INT_MASK, in hisi_femac_poll()
318 } while (ints & DEF_INT_MASK); in hisi_femac_poll()
322 hisi_femac_irq_enable(priv, DEF_INT_MASK & in hisi_femac_poll()
337 if (likely(ints & DEF_INT_MASK)) { in hisi_femac_interrupt()
338 writel(ints & DEF_INT_MASK, in hisi_femac_interrupt()
340 hisi_femac_irq_disable(priv, DEF_INT_MASK); in hisi_femac_interrupt()
477 hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK); in hisi_femac_net_open()
H A Dhip04_eth.c74 #define DEF_INT_MASK (RCV_INT | DEF_INT_ERR) macro
389 priv->reg_inten = DEF_INT_MASK; in hip04_mac_enable()
399 priv->reg_inten &= ~(DEF_INT_MASK); in hip04_mac_disable()
561 writel_relaxed(DEF_INT_MASK & ~RCV_INT, in hip04_mac_start_xmit()
671 writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT); in hip04_mac_interrupt()
688 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN); in hip04_mac_interrupt()
705 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN); in tx_done()
H A Dhix5hd2_gmac.c131 #define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \ macro
409 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); in hix5hd2_irq_enable()
658 } while (ints & DEF_INT_MASK); in hix5hd2_poll()
675 if (likely(ints & DEF_INT_MASK)) { in hix5hd2_interrupt()