1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /** 3 Support for Intel Camera Imaging ISP subsystem. 4 Copyright (c) 2010 - 2015, Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 */ 15 16 #ifndef _COMMON_ISP_CONST_H_ 17 #define _COMMON_ISP_CONST_H_ 18 19 /*#include "isp.h"*/ /* ISP_VEC_NELEMS */ 20 21 /* Binary independent constants */ 22 23 #ifndef NO_HOIST 24 # define NO_HOIST HIVE_ATTRIBUTE((no_hoist)) 25 #endif 26 27 #define NO_HOIST_CSE HIVE_ATTRIBUTE((no_hoist, no_cse)) 28 29 #define UNION struct /* Union constructors not allowed in C++ */ 30 31 #define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS 32 #define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 16) 33 #define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 32) 34 #define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES 35 36 #define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8) 37 #define BITS16_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 16) 38 39 #define ISP_NWAY_LOG2 6 40 41 /* ***************************** 42 * ISP input/output buffer sizes 43 * ****************************/ 44 /* input image */ 45 #define INPUT_BUF_DMA_HEIGHT 2 46 #define INPUT_BUF_HEIGHT 2 /* double buffer */ 47 #define OUTPUT_BUF_DMA_HEIGHT 2 48 #define OUTPUT_BUF_HEIGHT 2 /* double buffer */ 49 #define OUTPUT_NUM_TRANSFERS 4 50 51 /* GDC accelerator: Up/Down Scaling */ 52 /* These should be moved to the gdc_defs.h in the device */ 53 #define UDS_SCALING_N HRT_GDC_N 54 /* AB: This should cover the zooming up to 16MP */ 55 #define UDS_MAX_OXDIM 5000 56 /* We support maximally 2 planes with different parameters 57 - luma and chroma (YUV420) */ 58 #define UDS_MAX_PLANES 2 59 #define UDS_BLI_BLOCK_HEIGHT 2 60 #define UDS_BCI_BLOCK_HEIGHT 4 61 #define UDS_BLI_INTERP_ENVELOPE 1 62 #define UDS_BCI_INTERP_ENVELOPE 3 63 #define UDS_MAX_ZOOM_FAC 64 64 /* Make it always one FPGA vector. 65 Four FPGA vectors are required and 66 four of them fit in one ASIC vector.*/ 67 #define UDS_MAX_CHUNKS 16 68 69 #define ISP_LEFT_PADDING _ISP_LEFT_CROP_EXTRA(ISP_LEFT_CROPPING) 70 #define ISP_LEFT_PADDING_VECS CEIL_DIV(ISP_LEFT_PADDING, ISP_VEC_NELEMS) 71 /* in case of continuous the croppong of the current binary doesn't matter for the buffer calculation, but the cropping of the sp copy should be used */ 72 #define ISP_LEFT_PADDING_CONT _ISP_LEFT_CROP_EXTRA(SH_CSS_MAX_LEFT_CROPPING) 73 #define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS) 74 75 #define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \ 76 CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2)) 77 78 /* output (Y,U,V) image, 4:2:0 */ 79 #define MAX_VECTORS_PER_LINE \ 80 CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INTERNAL_WIDTH, ISP_VEC_NELEMS), \ 81 ISP_NUM_STRIPES, \ 82 ISP_LEFT_PADDING_VECS) 83 84 /* 85 * ITERATOR_VECTOR_INCREMENT' explanation: 86 * when striping an even number of iterations, one of the stripes is 87 * one iteration wider than the other to account for overlap 88 * so the calc for the output buffer vmem size is: 89 * ((width[vectors]/num_of_stripes) + 2[vectors]) 90 */ 91 #define MAX_VECTORS_PER_OUTPUT_LINE \ 92 CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) 93 94 /* Must be even due to interlaced bayer input */ 95 #define MAX_VECTORS_PER_INPUT_LINE CEIL_MUL((CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + ISP_LEFT_PADDING_VECS), 2) 96 #define MAX_VECTORS_PER_INPUT_STRIPE CEIL_ROUND_DIV_STRIPE(MAX_VECTORS_PER_INPUT_LINE, \ 97 ISP_NUM_STRIPES, \ 98 ISP_LEFT_PADDING_VECS) 99 100 /* Add 2 for left croppping */ 101 #define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2) 102 103 #define MAX_VECTORS_PER_BUF_LINE \ 104 (MAX_VECTORS_PER_LINE + DUMMY_BUF_VECTORS) 105 #define MAX_VECTORS_PER_BUF_INPUT_LINE \ 106 (MAX_VECTORS_PER_INPUT_STRIPE + DUMMY_BUF_VECTORS) 107 #define MAX_OUTPUT_Y_FRAME_WIDTH \ 108 (MAX_VECTORS_PER_LINE * ISP_VEC_NELEMS) 109 #define MAX_OUTPUT_Y_FRAME_SIMDWIDTH \ 110 MAX_VECTORS_PER_LINE 111 #define MAX_OUTPUT_C_FRAME_WIDTH \ 112 (MAX_OUTPUT_Y_FRAME_WIDTH / 2) 113 #define MAX_OUTPUT_C_FRAME_SIMDWIDTH \ 114 CEIL_DIV(MAX_OUTPUT_C_FRAME_WIDTH, ISP_VEC_NELEMS) 115 116 /* should be even */ 117 #define NO_CHUNKING (OUTPUT_NUM_CHUNKS == 1) 118 119 #define MAX_VECTORS_PER_CHUNK \ 120 (NO_CHUNKING ? MAX_VECTORS_PER_LINE \ 121 : 2 * CEIL_DIV(MAX_VECTORS_PER_LINE, \ 122 2 * OUTPUT_NUM_CHUNKS)) 123 124 #define MAX_C_VECTORS_PER_CHUNK \ 125 (MAX_VECTORS_PER_CHUNK / 2) 126 127 /* should be even */ 128 #define MAX_VECTORS_PER_OUTPUT_CHUNK \ 129 (NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \ 130 : 2 * CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \ 131 2 * OUTPUT_NUM_CHUNKS)) 132 133 #define MAX_C_VECTORS_PER_OUTPUT_CHUNK \ 134 (MAX_VECTORS_PER_OUTPUT_CHUNK / 2) 135 136 /* should be even */ 137 #define MAX_VECTORS_PER_INPUT_CHUNK \ 138 (INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \ 139 : 2 * CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \ 140 2 * OUTPUT_NUM_CHUNKS)) 141 142 #define DEFAULT_C_SUBSAMPLING 2 143 144 /****** DMA buffer properties */ 145 146 #define RAW_BUF_LINES ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2) 147 148 /* [isp vmem] table size[vectors] per line per color (GR,R,B,GB), 149 multiples of NWAY */ 150 #define ISP2400_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 151 CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 152 #define ISP2401_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 153 CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 154 /* [isp vmem] table size[vectors] per line for 4colors (GR,R,B,GB), 155 multiples of NWAY */ 156 #define SCTBL_VECTORS_PER_LINE \ 157 (SCTBL_VECTORS_PER_LINE_PER_COLOR * IA_CSS_SC_NUM_COLORS) 158 159 /*************/ 160 161 /* Format for fixed primaries */ 162 163 #define ISP_FIXED_PRIMARY_FORMAT IA_CSS_FRAME_FORMAT_NV12 164 165 #endif /* _COMMON_ISP_CONST_H_ */ 166