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Searched refs:DDR_TIMING_CFG_5 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dls1021aiot.h36 #define DDR_TIMING_CFG_5 0x03401400 macro
H A Dls1021atwr.h37 #define DDR_TIMING_CFG_5 0x03401400 macro
/openbmc/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c61 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
/openbmc/u-boot/board/freescale/ls1021atwr/
H A Dls1021atwr.c153 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()