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Searched refs:DDR_TIMING_CFG_2 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dls1021aiot.h33 #define DDR_TIMING_CFG_2 0x0040d120 macro
H A Dls1021atwr.h34 #define DDR_TIMING_CFG_2 0x0040d120 macro
/openbmc/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c58 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
/openbmc/u-boot/board/freescale/ls1021atwr/
H A Dls1021atwr.c150 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()