Home
last modified time | relevance | path

Searched refs:DDR_HMC_SEQ2CORE_INT_RESP_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_s10.h52 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) macro
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c114 DDR_HMC_SEQ2CORE_INT_RESP_MASK, in emif_reset()