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Searched refs:DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c345 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | in sdram_mmr_init_full()
349 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | in sdram_mmr_init_full()
356 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | in sdram_mmr_init_full()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_s10.h37 #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) macro