DDR_HMC_CORE2SEQ_INT_REQ (reference) in projects: openbmc

Searched refs:DDR_HMC_CORE2SEQ_INT_REQ (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A D	sdram_s10.h	`51 #define DDR_HMC_CORE2SEQ_INT_REQ 0xF macro`
/openbmc/u-boot/drivers/ddr/altera/
H A D	sdram_s10.c	`109 hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); in emif_reset()`