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Searched refs:DDR_CTL_PAD_DDR2_SEL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c104 #define DDR_CTL_PAD_DDR2_SEL BIT(6) macro
305 writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL, in ddr_init()