Searched refs:DDR_CLK_MHZ (Results 1 – 1 of 1) sorted by relevance
| /openbmc/u-boot/board/phytec/pcm051/ |
| H A D | board.c | 41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ macro
45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
92 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
135 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
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