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Searched refs:DDR_CFG1_REG (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dmt76xx.h22 #define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) macro
H A Dlowlevel_init.S257 li t1, DDR_CFG1_REG
306 li t5, DDR_CFG1_REG