Searched refs:DDR_BASE_CS_OFF (Results 1 – 3 of 3) sorted by relevance
90 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro414 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_sdram_debug_show_orion()679 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()711 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_save_cpu_target()714 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i), in mvebu_mbus_default_save_cpu_target()
15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
78 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro326 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()