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Searched refs:DDRPHY_SHU1_PLL8 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c100 #define DDRPHY_SHU1_PLL8 0x0da0 macro
349 writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8); in mtk_ddr3_init()
359 writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8); in mtk_ddr3_init()