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Searched refs:DDRPHY_SHU1_PLL1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c95 #define DDRPHY_SHU1_PLL1 0x0d84 macro
361 writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1); in mtk_ddr3_init()