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Searched refs:DDRPHY_SHU1_B0_DQ5 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c82 #define DDRPHY_SHU1_B0_DQ5 0x0c14 macro
305 writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); in mtk_ddr3_init()
450 writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); in mtk_ddr3_init()