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Searched refs:DDRPHY_PLL1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c22 #define DDRPHY_PLL1 0x0000 macro
335 writel(0x0, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
386 writel(0x80010000, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
408 writel(0x80000000, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()